Mirrors Ch3: Light Load — How Closed-Loop Responds

In Ch3, R=100Ω caused open-loop output to rise to 8.2V. Under same conditions, closed-loop output≈6.3V — error reduced from +37% to +4%.

Recall Ch3 Lesson 1: load changes from 10Ω to 100Ω, open-loop enters DCM, output rises to 8.2V. Now the same conditions, but the circuit has a feedback loop — divider senses Vout, comparator auto-adjusts PWM width.

Result: closed-loop output≈6.3V. Much better than open-loop 8.2V — deviation compressed from 2.2V to 0.3V, 88% improvement.

What is feedback doing? Vout rises → divider output rises → error amplifier (VCVS) output decreases → comparator duty cycle decreases → D drops → Vout pulled back. High-gain error amplifier makes correction more forceful.

Why is reference v3 set to 0.45V? Design derivation: the divider at target Vout=6V gives Vfb = 6/12 = 0.5V. The VCVS (gain=-10) computes control voltage = |gain| × (Vfb − Vref) = 10 × (0.5 − 0.45) = 0.5V. This 0.5V compared against the sawtooth (0–1V) produces exactly 50% duty cycle → D=50% → Vout = 0.5×12 = 6V. Formula: Vref = Vfb_target − D_target/|gain| = 0.5 − 0.5/10 = 0.45V.