Add R-C compensation around the error amplifier, using a zero to cancel the LC pole phase lag while keeping high DC gain.
The core compensation concept: add R-C networks in the error amplifier feedback path to reshape the loop gain's frequency response. The Type-II compensator (also called PI + pole compensation) has one zero and one high-frequency pole, combined with an integrator (pole at origin): very high DC gain → zero steady-state error; zero boosts mid-frequency phase → adequate PM; high-frequency pole attenuates switching noise.
Circuit parameters: VCVS gain = 1000 (emulating an opamp), R_in = 10kΩ, R_comp = 10kΩ, C_comp1 = 100nF (series with R_comp), C_comp2 = 1.5nF (parallel), Rdc = 1MΩ (weak DC bias path, negligible AC effect). Zero fz = 1/(2π×R_comp×C_comp1) ≈ 159Hz — below LC resonance, 'pulling up' phase before crossover. High-frequency pole fp ≈ 1/(2π×R_comp×C_comp2) ≈ 10.6kHz — well above crossover, only for noise attenuation.
Result: run the simulation — output is stable at ~6V, no oscillation. Compare with L1: same high gain, but with compensation it's perfectly stable. Compare with Ch4: DC accuracy far exceeds proportional control. This is 'having your cake and eating it too': high gain + stability.
R_comp=10k, C_comp1=100nF (fz≈159Hz), C_comp2=1.5nF (fp≈10.6kHz). Stable and accurate.
After reading this section, run the simulation and observe the waveforms. To explore further, open the example in a standalone page.